Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

RENESAS

瑞萨

Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

RENESAS

瑞萨

Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

RENESAS

瑞萨

OCTAL D TYPE FLIP FLOP

DESCRIPTION The M54/74HC377 is a high speed CMOS OCTALD-TYPE FLIP FLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Information at the D inputs meeting the setup time requirements is transferred to the

文件：252.71 Kbytes 页数：11 Pages

STMICROELECTRONICS

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