3.3-V Phase-lock Loop Clock Driver

Description The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronou

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3.3-V Phase-lock Loop Clock Driver

Description The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronou

文件：42.83 Kbytes 页数：11 Pages

HITACHIHitachi Semiconductor

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3.3-V Phase-lock Loop Clock Driver

Description The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronou

文件：228.2 Kbytes 页数：8 Pages

RENESAS

瑞萨

DIP

HIT

上传：深圳市佳鑫美电子科技有限公司

DIP-14

HIT

上传：深圳市昌和盛利电子有限公司