H5AN8G8NAFR中文资料DDR4 SDRAM数据手册SK hynix规格书

描述 Description

The H5AN8G4NAFR-xxC, H5AN8G8NAFR-xxC and H5AN8G6NAFR-xxC are a 8Gb CMOS Double Data Rate IV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 8Gb DDR4 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

特性 Features

• VDD=VDDQ=1.2V +/- 0.06V
• Differential Data Strobe (DQS, DQS)
• DM masks write data-in at the both rising and falling edges of the data strobe
• Programmable CAS latency 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20 supported
• Programmable CAS Write latency (CWL) = 9, 10, 11, 12, 14, 16, 18
• BL switch on the fly
• Average Refresh Cycle   (Tcase of 0  oC~ 95 oC)                                                         - 7.8 µs at 0oC ~ 85 oC                                                                 - 3.9 µs at 85oC ~ 95 oC
• Driver strength selected by MRS
• Two Termination States such as RTT_PARK and RTT_NOM switchable by ODT pin
• ZQ calibration supported
• Write Levelization supported
• This product in compliance with the RoHS directive.
• Write CRC is supported at all speed grades
• TCAR(Temperature Controlled Auto Refresh) mode is supported
• Fine Granularity Refresh is supported
• Geardown Mode(1/2 rate, 1/4 rate) is supported
• Self Refresh Abort is supported
• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
• DBI(Data Bus Inversion) is supported(x8)