GTL2010

10-bit bidirectional low voltage translator

Generaldescription TheGunningTransceiverLogic-TransceiverVoltageClamps(GTL-TVC)providehigh-speedvoltagetranslationwithlowON-stateresistanceandminimalpropagationdelay.TheGTL2010provides10NMOSpasstransistors(SnandDn)withacommongate(GREF)andareferencetransisto

ETC

GTL2010

NXP bidirectional low-voltage translators

Lowcostbidirectionalvoltagetranslationwithoutdirectionalcontrol Unlikelevel-shiftingbusswitches,whichonlytranslatebetweenfixedvoltages,thesebidirectionallow-voltagetranslatorscantranslateanyvoltagebetween1and5Vtoanyothervoltagebetween1and5V.Theyalsore

ETC

GTL2010

10-bit GTL Processor Voltage Clamp

Description Withinthesemiconductorworld,therearemanyI/Ostandardsthathavedifferentvoltagelevelrequirementsfortheinputvoltage(VIHorVIL)andoutputvoltage(VOHorVOL)typicallybasedonthedeviceoperatingvoltage.Thesevoltagelevelsdefinehowthedevicecommunicateswith

PHI

GTL2010

10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR

GTL2010

10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR;

GTL2010

Smart, simple solutions for the 12 most common design concerns

ETC

GTL2010BS

10-bit bidirectional low voltage translator

Generaldescription TheGunningTransceiverLogic-TransceiverVoltageClamps(GTL-TVC)providehigh-speedvoltagetranslationwithlowON-stateresistanceandminimalpropagationdelay.TheGTL2010provides10NMOSpasstransistors(SnandDn)withacommongate(GREF)andareferencetransisto

ETC

GTL2010BS

10位双向低电压变换器; 10-bit bidirectional low voltage translator\nAllows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels\nProvides bidirectional voltage translation with no direction pin\nLow 6.5 Ω ON-state resistance (Ron) between input and output pins (Sn/Dn)\nSupports hot insertion\nNo power supply required: will not latch up\n5 V tolerant inputs\nLow standby current\nFlow-through pinout for ease of printed-circuit board trace routing\nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101\nPackages offered: TSSOP24, HVQFN24\n;

The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2010 provides 10 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1.0 V and 5.0 V without use of a direction pin.\nWhen the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control.\nAll transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, SREF and DREF can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator's transistors provide excellent ESD protection to lower voltage devices and at the same time protect less ESD-resistant devices.\n

恩XP

GTL2010BS-T

NXP bidirectional low-voltage translators

Lowcostbidirectionalvoltagetranslationwithoutdirectionalcontrol Unlikelevel-shiftingbusswitches,whichonlytranslatebetweenfixedvoltages,thesebidirectionallow-voltagetranslatorscantranslateanyvoltagebetween1and5Vtoanyothervoltagebetween1and5V.Theyalsore

ETC

GTL2010PW

10-bit GTL Processor Voltage Clamp

Description Withinthesemiconductorworld,therearemanyI/Ostandardsthathavedifferentvoltagelevelrequirementsfortheinputvoltage(VIHorVIL)andoutputvoltage(VOHorVOL)typicallybasedonthedeviceoperatingvoltage.Thesevoltagelevelsdefinehowthedevicecommunicateswith

PHI