FDC6302P中文资料仙童半导体数据手册PDF规格书

General Description

These Dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switchimg applications. Since bias resistors are not required this one P-Channel FET can replace several digital transistors with different bias resistors like the IMBxA series.

特性 Features

■ -25 V, -0.12 A continuous, -0.5 A Peak. RDS(ON) = 13 Ω @ VGS= -2.7 V RDS(ON) = 10 Ω @ VGS = -4.5 V.

■ Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V.

■ Gate-Source Zener for ESD ruggedness. >6kV Human Body Model

■ Replace multiple PNP digital transistors (IMHxA series) with one DMOS FET.