丝印：EA32882B；Package：NFBGA；28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • JEDEC SSTE32882 Compliant • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distribu

文件：777.11 Kbytes 页数：13 Pages

TI

德州仪器

丝印：EA32882B；Package：NFBGA；28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • JEDEC SSTE32882 Compliant • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distribu

文件：777.11 Kbytes 页数：13 Pages

TI

德州仪器