DSP56603EVM中文资料Evaluation Module数据手册恩XP规格书

描述 Description

Overview This product has been designated as an \"End Of Life Buy\" and is not recommended for NEW designs The DSP56603 Evaluation Module is designed as a low-cost platform for developing real-time software and hardware products to support a new generation of applications in wireless and wireline communications, multimedia, speech, control, and general digital signal processing. The user can download software to on-chip or on-board Ram, then run and debug it. The user can also connect hardware, such as external memories and A/D or D/A converters, for product development. The 16-bit precision of the DSP56603 Digital Signal Processor (DSP) combined with the on-board 32 K of external SRAM and Crystal Semiconductor's CS4215 stereo, CD-quality, audio codec makes the DSP56603EVM ideal for implementing and demonstrating many communications and speech processing algorithms, as well as for learning the architecture and instruction set of the DSP56600 family processor.

特性 Features

High Performance DSP56600 Core
•60 Million Instructions Per Second (MIPS) with a 60 MHz clock (at 2.7 volts)
•Object-code compatible with the DSP56000 and DSP56300 cores
•Highly parallel instruction set
•Fully pipelined 16 X 16 parallel Multiplier-Accumulator (MAC)
•Two 40-bit parallel barrel shifter
•Position Independent Code (PIC) Support
•Unique DSP addressing modes
•On-chip memory-expandable hardware stack
•Nested hardware DO loops
•Fast auto-return interrupts
•On-chip Phase Lock Loop (PLL)
•On-Chip Emulation (OnCE) Module
•JTAG port
•Address Tracing mode reflects internal Program RAM accesses at external port
•On-chip support for software patching and enhancements

On-Chip Memories
•Program RAM, X-data RAM, and Y data RAM size is programmable:
Switch ModeProgram RAM SizeX Data RAM SizeY Data RAM Size
disabled16.5 K X 24-bit8 K X 16-bit8 K X 16-bit
enabled11.5 K X 24-bit10.5 K X 16-bit10.5 K X 16-bit
•3 K X 24-bit bootstrap ROM

Off-Chip Memory Expansion
•Program memory expansion to one memory space of 64 K X 24-bit words
On-Chip Peripherals
•Enhanced DSP56600-like 8-bit parallel Host Interface (HI08)
•Two Synchronous Serial Interfces (SSIO and SSI1)
•Triple timer module
•As many as thirty-four programmable General Purpose Input/Output (GPIO) pins, depending on which peripherals are enabled
Reduced Power Dissipation
•Very low power CMOS design
•Wait and Stop low power standby modes
•Fully static logic, operation from the device maximum frequency down to DC