DSP56603数据手册恩XP中文资料规格书

描述 Description

Overview This product has been designated as an \"End Of Life Buy\" and is not recommended for NEW designs The DSP56603 is designed specifically for low-power digital handset wireless applications and can perform a wide variety of fixed-point digital signal processing algorithms. Because of its large RAM size, the DSP56603 supports rapid code development, shortening time to market. The ROM-based DSP56602 is the more cost-effective solution for mass production.

特性 Features

Digital Signal Processing Core


• High-performance DSP56600 core

• Up to 60 Million Instructions Per Second (MIPS) at 2.7 V-3.3 V

• Fully pipelined 16 x 16-bit parallel Multiplier Accumulator (MAC)

• Two 40-bit accumulators including extension bits

• 40-bit parallel barrel shifter

• Highly parallel instruction set with unique DSP addressing modes

• Code-compatible with the DSP56300 core

• Position-independent code support

• Nested hardware DO loops

• Fast auto-return interrupts

• On-chip support for software patching and enhancements

• On-chip Phase Lock Loop (PLL) circuit

• Real-time trace capability via external address bus

• On-Chip Emulation (OnCETM) module

• JTAG port


Memory

• Switch mode reconfigures program, X-data, and Y-data RAM sizes

• Default configuration (Switch mode off)




• 16.5 K x 24-bit Program RAM

• 8 K x 16-bit X-data RAM

• 8 K x 16-bit Y-data RAM

• Switch mode on




• 11.5 K x 24-bit Program RAM

• 10.5 K x 16-bit X-data RAM

•10.5 K x 16-bit Y-data RAM

• 3 K x 24-bit Program ROM

• Off-chip expansion for both program fetch and program data transfers

• Glueless interface to external SRAM memories
Peripheral Circuits

• Three dedicated General Purpose Input/Output (GPIO) pins and up to thirty
one additional GPIO pins (user-selectable as peripherals or GPIO pins)

• Host interface (HI) support: One 8-bit parallel port (or up to sixteen
additional GPIO pins)

• Direct interface to Motorola HC11, Hitachi H8, 8051 family, Thomson
P6 family

• Minimal logic interface to standard ISA bus, Motorola 68K family, and
Intel x86 microprocessor family.




• Synchronous Serial Interface (SSI) support: Two 6-pin ports (or twelve
additional GPIO pins)

• Supports serial devices with one or more industry-standard codecs,
other DSPs, microprocessors, and Motorola SPI-compliant peripherals

• Independent transmitter and receiver sections and a common SSI clockgenerator

• Network mode using frame sync and up to 32 time slots

• 8-bit, 12-bit, and 16-bit data word lengths




• Three programmable timers (or up to three additional GPIO pins)

• Three external interrupt/mode control lines

• One external reset pin for hardware reset

Energy Efficient Design

• Operating voltage range: 1.8 V to 3.3 V

• Very low power CMOS design

•


• Low power Wait for interrupt standby mode

• Ultra low power Stop standby mode

• Fully static, HCMOS design for operating frequencies from 60 MHz down to
DC

•Special power management circuitry