DSP56001A中文资料24-bit Digital Signal Processor数据手册恩XP规格书

描述 Description

Overview This product is designated as an \"end of life buy.\" Final orders must be placed by July 30, 2002.

特性 Features

Digital Signal Processing Core
•Efficient, object code compatible, 24-bit
•Up to 16.5 Million Instructions Per Second (MIPS)—60.6
•Up to 99 Million Operations Per Second (MOPS)
•Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898
•Highly parallel instruction set with unique DSP addressing modes
•Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
•56-bit addition/subtraction in 1
•Fractional arithmetic with support for multiprecision arithmetic
•Hardware nested DO loops •Zero-overhead
•Four 24-bit internal data buses and three
•On-chip modified Harvard architecture permitting simultaneous accesses to
•512 x 24-bit on-chip Program RAM and 64 x 24-bit bootstrap ROM
•Two 256 x 24-bit on-chip data ROMs containing sine, A-law and m-law tables
•Bootstrap loading from external data bus or Host Interface
•Byte-wide Host Interface (HI) with Direct Memory Access (DMA) support
•8-, 12-, 16-, and 24-bit word sizes •Up to 32 software-selectable
•Serial Communication Interface (SCI) for full-duplex asynchronous communications
•Double-buffered peripherals
•Two external interrupt request pins
•Power-saving Wait and Stop modes
•88-pin Ceramic Pin Grid Array (PGA) package; 13 x 13 array
•132-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 22 x 22 x 4
•5 V power supply