DSP56001A数据手册恩XP中文资料规格书

描述 Description

Overview This product is designated as an \"end of life buy.\" Final orders must be placed by July 30, 2002.

特性 Features

Digital Signal Processing Core
•Efficient, object code compatible, 24-bit
56000 family DSP engine
•Up to 16.5 Million Instructions Per Second (MIPS)—60.6
ns instruction cycle at 33 MHz
•Up to 99 Million Operations Per Second (MOPS)
at 33 MHz
•Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898
clocks
•Highly parallel instruction set with unique DSP addressing modes
•Two
56-bit accumulators including extension byte
•Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
•Double precision 48 x 48-bit multiply with 96-bit result in 6 instruction
cycles
•56-bit addition/subtraction in 1
instruction cycle •Fractional arithmetic with support for multiprecision arithmetic
•Hardware support for block-floating point FFT
•Hardware nested DO loops •Zero-overhead
fast interrupts (2 instruction cycles)
•Four 24-bit internal data buses and three
16-bit internal address buses for maximum information transfer on-chip
Memory

•On-chip modified Harvard architecture permitting simultaneous accesses to
program and two data memories
•512 x 24-bit on-chip Program RAM and 64 x 24-bit bootstrap ROM
•Two 256 x 24-bit on-chip data RAMs
•Two 256 x 24-bit on-chip data ROMs containing sine, A-law and m-law tables
•External memory expansion with 16-bit address and 24-bit data buses
•Bootstrap loading from external data bus or Host Interface
Peripheral and Support Circuits

•Byte-wide Host Interface (HI) with Direct Memory Access (DMA) support
•Synchronous Serial Interface (SSI) to communicate with codecs and synchronous
serial devices
•8-, 12-, 16-, and 24-bit word sizes •Up to 32 software-selectable
time slots in Network mode
•Serial Communication Interface (SCI) for full-duplex asynchronous communications
•On-chip peripheral registers memory mapped in data memory space
•Double-buffered peripherals
•Up to twenty-four General Purpose I/O (GPIO) pins
•Two external interrupt request pins
Miscellaneous

•Power-saving Wait and Stop modes
•Fully static, HCMOS design for operating frequencies from 33 MHz down to
4 MHz
•88-pin Ceramic Pin Grid Array (PGA) package; 13 x 13 array
•132-pin Plastic Quad Flat Pack (PQFP) surface-mount package; 24 x 24 x 4
mm
•132-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 22 x 22 x 4
mm
•5 V power supply