DSP56300FM/AD中文资料恩智浦数据手册PDF规格书

FEATURES

Hardware

• 24-bit DSP56307 Digital Signal Processor

– High -Performance DSP56300 core

• 100 Million Instructions Per Second (MIPS) with a 100-MHz clock at 2.5-V core and

3.3 V I/O

• Object code compatible with the DSP56000 core

• Highly-parallel instruction set

• Data Arithmetic Logic Unit (ALU)

• Fully pipelined 24-x 24-bit parallel multiplier-accumulator

• 56-bit parallel barrel shifter

• Conditional ALU instructions

• 24-bit or 16-bit arithmetic support under software control

• Position Independent Code (PIC) support

• Addressing modes optimized for DSP applications (including immediate offsets)

• On-chip memory-expandable hardware stack

• Nested hardware DO loops

• Fast auto-return interrupts

• On-chip concurrent six-channel DMA controller

• On-chip Phase-Locked Loop (PLL)

• On-Chip Emulation (OnCEÔ) module

• JTAG port

• Address tracing mode reflects internal program RAM accesses at the external port

– Enhanced Filter Coprocessor (EFCOP)

• On-chip filtering and echo-cancellation coprocessor runs in parallel to the DSP core