DS_S5T8702中文资料三星数据手册PDF规格书

INTRODUCTION

This FLEXTM Alphanumeric Decoder II date sheet describes the operation of the S5T8702.

The S5T8702 simplifies implementation of a FLEXTM paging device by interfacing with any of several off-the-shelf paging receivers and any of several off-the-shelf host microcontroller/microprocessors. Its primary function is to process information received and demodulated from a FLEX radio paging channel, select messages addressed to the paging device and communicate the message information to the host. The S5T8702 also operates the paging receiver in an efficient power consumption mode and enables the host to operate in a low power mode when monitoring a signal channel for message information.

FEATURES

• FLEXTM paging protocol decoder

• 16 programmable user address words

• 16 fixed temporary addresses

• 16 operator messaging addresses

• 1600,3200,and 6400bps(bits per second) decoding

• Any-phase or single-phase decoding

• Uses standard Serial Peripheral Interface (SPI) in slave mode

• Allow low current STOP mode operation of host processor

• Highly programmable receiver control

• Real time clock time base

• FLEX fragmentation and group messaging support

• Real time clock over-the-air update support

• Compatible with synthesized receivers

• Low Battery Indication(External detector)

• 28 used pins (32-pin package standard)

• Internal demodulator and data slicer

• Improved battery savings via partial correlation and intermittent receiver clock

• Full support for revision 1.9 of the FLEX protocol

• 32-pin LQFP package

• Supply voltage: 1.8 to 3.6V

• Operating frequency: 76.8kHz or 160kHz