48 位 LVDS 通道链接解串器，具备 33MHz 至 112MHz 输入时钟支持

The DS90CR483A transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input data are sampled a • Up to 5.38 Gbits/sec Bandwidth\n• 33 MHz to 112 MHz Input Clock Support \n• LVDS SER/DES Reduces Cable and Connector Size\n• Pre-emphasis Reduces Cable Loading Effects\n• DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion\n• Cable Deskew of +/−1 LVDS Data Bit Time (up to 8;

TI

德州仪器

Package：100-TQFP；包装：托盘 功能：解串器 类别：集成电路（IC） 串行器，解串器 描述：IC DESERIALIZER 48BIT 100TQFP

TI

德州仪器

Package：100-TQFP；包装：卷带（TR） 功能：解串器 类别：集成电路（IC） 串行器，解串器 描述：IC DESERIALIZER 48BIT 100TQFP

TI

德州仪器