DS90CR288数据手册集成电路（IC）的专用规格书PDF

描述 Description

General Description
The DS90CR287 (see DS90CR287/288A datasheet) transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR288 receiver converts the four LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 75 MHz, 28 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75 MHz clock, the data throughput is 2.10 Gbit/s (262.5 Mbytes/sec). Complete specifications for the DS90CR287 are located in the DS90CR287/DS90CR288A datasheet. The DS90CR287 supports clock rates from 20 to 85 MHz.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

特性 Features

■ 20 to 75 MHz shift clock support
■ 50% duty cycle on receiver output clock
■ Best-in-Class Set & Hold Times on TxINPUTs and RxOUTPUTs
■ Low power consumption
■ Tx + Rx Powerdown mode <400µW (max)
■ ±1V common-mode range (around +1.2V)
■ Narrow bus reduces cable size and cost
■ Up to 2.10 Gbps throughput
■ Up to 262.5 Mbytes/sec bandwidth
■ 345 mV (typ) swing LVDS devices for low EMI
■ PLL requires no external components
■ Rising edge data strobe
■ Compatible with TIA/EIA-644 LVDS standard
■ Low profile 56-lead TSSOP package