DS90CR218数据手册集成电路（IC）的专用规格书PDF

描述 Description

General Description
The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR218 receiver converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75 MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

特性 Features

■ 20 to 75 MHz shift clock support
■ 50% duty cycle on receiver output clock
■ Best–in–Class Set & Hold Times on TxINPUTs and RxOUTPUTs
■ Low power consumption
■ Tx + Rx Power-down mode <400µW (max)
■ ±1V common mode range (around +1.2V)
■ Narrow bus reduces cable size and cost
■ Up to 1.575 Gbps throughput
■ Up to 197 Megabytes/sec bandwidth
■ 345 mV (typ) swing LVDS devices for low EMI
■ PLL requires no external components
■ Rising edge data strobe
■ Compatible with TIA/EIA-644 LVDS standard
■ Low profile 48-lead TSSOP package