DS3100数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multiprotocol BITS/SSU receivers and 14 input clocks, the device directly accepts both external timing and line timing from a large number of line cards. All input clocks are continuously monitored for frequency accuracy and activity. Any two of the input clocks can be selected as the references for the two core DPLLs. The T0 DPLL complies with the Stratum 2, 3E, 3, 4E and 4 requirements of GR1244, GR-253, G.812 Types I–IV, G.813 and G.8262. From the output of the core DPLLs, a wide variety of output clock frequencies and frame pulses can be produced simultaneously on the 11 output clock pins. Two DS3100 devices can be configured in a master/slave arrangement for timing card equipment protection.

The DS3100 registers and I/O pins are backward compatible with Semtech's ACS8520 and ACS8530 timing card ICs.

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特性 Features

Synchronization Subsystem for Stratum 2, 3E, 3, 4E and 4 plus SMC, SEC and EEC
• Meets Requirements of GR-1244 Stratum 2–4, GR-253, G.812 Types I–IV, G.813 and G.8262
• Stratum 2, 3E or 3 Holdover Accuracy with Suitable External Oscillator
• Programmable Bandwidth, 0.5mHz to 70Hz
• Hitless Reference Switching on Loss of Input
• Phase Build-Out and Transient Absorption
• Locks to and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.8261
14 Input Clocks
• 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any Multiple of 8kHz Up to 125MHz
• Two LVDS/LVPECL/CMOS/TTL Inputs Accept Nx8kHz Up to 125MHz Plus 155.52MHz
• Two 64kHz Composite Clock Receivers
• Continuous Input Clock Quality Monitoring
• Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
• Five CMOS/TTL Outputs Drive Any Internally Produced Clock Up to 77.76MHz
• Two LVDS Outputs Each Drive Any Internally Produced Clock Up to 311.04MHz
• One 64kHz Composite Clock Transmitter
• One 1.544MHz/2.048MHz Output Clock
• Two Sync Pulses: 8kHz and 2kHz
• Output Clock Rates Include 2kHz, 8kHz, NxDS1, NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz, 38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz, 125MHz, 155.52MHz, 311.04MHz
Two Multiprotocol BITS/SSU Transceivers
• Receive and Transmit DS1, E1, 2048kHz, and 6312kHz Timing Signals
• Insert and Extract SSM Messages (DS1, E1)
• Automatically Invalidate Clocks on LOS, OOF, AIS, and Other Defects
Internal Compensation for Master Clock Oscillator Frequency Accuracy
Processor Interface: 8-Bit Parallel or SPI Serial
1.8V Operation with 3.3V I/O (5V Tolerant)
Applications/Uses
• Digital Cross-Connects
• DSLAMs
• Service Provider Routers
• SONET/SDH ADMs, MSPPs, and MSSPs

简介

DS3100属于集成电路（IC）的应用特定时钟/定时。由制造生产的DS3100应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。