DS2064S-200中文资料亚德诺数据手册PDF规格书

DESCRIPTION

The DS2064 is a 65536–bit low power, fully static random access memory organized as 8192 words by eight bits using CMOS technology. The device operates from a single power supply with a voltage input between 4.5V and 5.5V. The chip enable inputs (CE1 and CE2) are used for device selection and can be used in order to achieve the minimum standby current mode, which facilitates both battery operate and battery backup applications. The device provides fast access time of 200 ns and is most suitable for low power applications where battery operation or battery backup for nonvolatility are required. The DS2064 is a JEDEC–standard 8K x 8 SRAM and is pin–compatible with ROM and EPROM of similar density.

FEATURES

• Low power CMOS design

• Standby current

50 nA max at tA = 25°C VCC = 3.0V

100 nA max at tA = 25°C VCC = 5.5V

1 µA max at tA = 60°C VCC = 5.5V

• Full operation for VCC = 4.5V to 5.5V

• Data Retention Voltage = 5.5V to 2.0V

• Access time equals 200 ns at 5.0V

• Operating temperature range of –40°C to +85°C

• Full static operation

• TTL compatible inputs and outputs

• Available in 28–pin DIP and 28–pin SOIC packages

• Suitable for both battery operated and battery backup applications