DRA79中文资料适用于音频放大器且带 DSP 的 300MHz ARM Cortex-A15 SoC 处理器数据手册TI规格书

描述 Description

The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mmspacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array(BGA) package.
The architecture is designed to deliver high-performance concurrencies for automotiveco-processor, hybrid radio and amplifier applications in a cost-effective solution, providing fullscalability from the DRA75x (\"Jacinto 6 EP\" and \"Jacinto 6 Ex\"), DRA74x \"Jacinto 6\", DRA72x\"Jacinto 6 Eco\", and DRA71x \"Jacinto 6 Entry\" family of infotainment processors.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon™extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keepcontrol functions separate from other algorithms programmed on the DSP and coprocessors, thusreducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP,including C compilers and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported securityfeatures, including support for secure boot, debug security and support for trusted executionenvironment are available on High-Security (HS) devices. For more information about HS devices,contact your TI representative.
The DRA79x Jacinto 6 RSP (Radio Sound Processor) device family is qualified accordingto the AEC-Q100 standard.
The device features a simplified power supply rail mapping which enables lower costPMIC solutions.
The DRA79x processor isoffered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals)with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.
The architecture is designed to deliver high-performance concurrencies for automotiveapplications in a cost-effective solution, providing full scalability from the DRA75x (\"Jacinto 6EP\" and \"Jacinto 6 Ex\"), DRA74x \"Jacinto 6\" and DRA72x \"Jacinto 6 Eco\" family of infotainmentprocessors.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon™extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keepcontrol functions separate from other algorithms programmed on the DSP and coprocessors, thusreducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP,including C compilers and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported securityfeatures, including support for secure boot, debug security and support for trusted executionenvironment are available on High-Security (HS) devices. For more information about HS devices,contact your TI representative.
The DRA79x Jacinto 6Entry processor family is qualified according to the AEC-Q100 standard.
The device features are simplified power supply rail mapping which enables lower costPMIC solutions.

特性 Features

• Architecture Designed for Infotainment Co-Processor Applications, Hybrid Radio and Amplifier Applications
• C66x Floating-Point VLIW DSP
• Fully Object-Code Compatible With C67x and C64x+
• Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle
• Up to 512KB of On-Chip L3 RAM
• DDR3/DDR3L Memory Interface (EMIF) Module
• Supports up to DDR-1333 (667 MHz)
• Dual Arm® Cortex®-M4 Image Processing Units (IPU)
• DisplayController With DMA Engine and Up to Three Pipelines
• Video Processing Engine (VPE)
• One Video Input Port (VIP) Module
• Support for up to FourMultiplexed Input Ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA) Controller
• 2-Port Gigabit Ethernet (GMAC)
• Up to Two External Ports
• Sixteen 32-Bit General-Purpose Timers
• 32-Bit MPU Watchdog Timer
• Six High-Speed Inter-Integrated Circuit (I2C) Ports
• Ten Configurable UART/IrDA/CIR Modules
• Four Multichannel Serial Peripheral Interfaces (McSPI)
• Media Local Bus Subsystem (MLBSS)
• Eight Multichannel Audio Serial Port (McASP) Modules
• High-Speed USB 2.0 Dual-Role Device
• Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
• One 2-lane Gen2-Compliant Port
• Dual Controller Area Network (DCAN) Modules
• CAN 2.0BProtocol
• MIPI® CSI-2 Camera Serial Interface
• Device Security Features
• Hardware Crypto Accelerators andDMA
• JTAG Lock
• Secure ROM and Boot
• Power, Reset, and Clock Management
• On-Chip Debug With CTools Technology
• 17 mm × 17 mm, 0.65-mm Pitch, 538-Pin BGA (CBD)
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