DRA785中文资料适用于音频放大器且具有 2 个 1000MHz C66x DSP 和 2 个双核 Arm Cortex-M4 的 SoC 处理器数据手册TI规格书

描述 Description

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x (\"Jacinto 6 EP\" and \"Jacinto 6 Ex\"), DRA74x \"Jacinto 6\", DRA72x \"Jacinto 6 Eco\", and DRA71x \"Jacinto 6 Entry\" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x (\"Jacinto 6 EP\" and \"Jacinto 6 Ex\"), DRA74x \"Jacinto 6\", DRA72x \"Jacinto 6 Eco\", and DRA71x \"Jacinto 6 Entry\" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

特性 Features

• Architecture designed for infotainment applications
• Fully object-code compatible with C67x and C64x+
• Up to 512kB of on-chip L3 RAM
• Memory Interface (EMIF) module
• Supports DDR2 up to DDR-800
• Dual Arm® Cortex®-M4 (IPU)
• Embedded Vision Engine (EVE)
• Display subsystem
• CVIDEO / SD-DAC TV analog composite output
• On-chip temperature sensor that is capable of generating temperature alerts
• Enhanced Direct Memory Access (EDMA) controller
• Controller Area Network (DCAN) module
• Modular Controller Area Network (MCAN) module
• Eight 32-bit general-purpose timers
• Four Multichannel Serial Peripheral Interfaces (McSPI)
• Two Inter-Integrated Circuit (I2C™) ports
• Secure Digital Input Output Interface (SDIO)
• Power, reset, and clock management
• Automotive AEC-Q100 qualified
• Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
• PWMSS
• Full-HD video (1920 × 1080p, 60 fps)
• GPIOs when not used for video
• Video Input Port (VIP) module
• Support for up to 4 multiplexed input ports