DRA72数据手册TI中文资料规格书

描述 Description

DRA72x (\"Jacinto 6 Eco\") infotainment applications processors are developed on the samearchitecture as Jacinto 6 devices to meet the intense processing needs of the moderninfotainment-enabled automobile experiences.
DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatibleacross the family, allowing Original-Equipment Manufacturers (OEMs) and Original-DesignManufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition,audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performancethrough the maximum flexibility of a fully integrated mixed processor solution.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU withNeon™ extensions and a TI C66x VLIW floating-point DSPcore. The Arm processor lets developers keep control functions separate from other algorithmsprogrammed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP,including C compilers and a debugging interface for visibility into source code execution.
The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100standard.

特性 Features

• Architecture Designed for Infotainment Applications
• Video, Image, and Graphics Processing Support
• Full-HD Video (1920 × 1080p, 60 fps)
• MultipleVideo Input and Video Output
• 2D and 3DGraphics

• Arm® Cortex®-A15 Microprocessor Subsystem

• C66x Floating-Point VLIW DSP
• Fully Object-Code Compatible With C67x and C64x+

• Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle

• Up to 512KB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• DDR3/DDR3L Memory Interface (EMIF) Module
• Supports up to DDR3-1333 (667 MHz)
• Up to 2GBAcross Single Chip Select

• Dual Arm® Cortex®-M4 Image Processing Units (IPU)
• IVA-HD Subsystem
• Display Subsystem
• Display Controller With DMA Engine and up to ThreePipelines
• HDMI™ Encoder: HDMI1.4a and DVI 1.0 Compliant

• 2D-Graphics Accelerator (BB2D) Subsystem
• Vivante® GC320Core

• Video Processing Engine (VPE)
• Single-Core PowerVR™ SGX544 3D GPU

• One Video Input Port (VIP) Module
• Support for up to FourMultiplexed Input Ports


• General-Purpose Memory Controller (GPMC)

• Enhanced Direct Memory Access (EDMA) Controller

• 2-Port Gigabit Ethernet (GMAC)
• Up to Two External Ports

• Sixteen 32-Bit General-Purpose Timers

• 32-Bit MPU Watchdog Timer

• Six High-Speed Inter-Integrated Circuit (I2C) Ports
• HDQ™/1-Wire® Interface
• Ten Configurable UART/IrDA/CIR Modules

• Four Multichannel Serial Peripheral Interfaces (McSPI)
• Quad SPI Interface (QSPI)
• Media Local Bus Subsystem (MLBSS)
• Real-Time Clock Subsystem (RTCSS)
• SATA Interface

• Eight Multichannel Audio Serial Port (McASP) Modules
• SuperSpeed USB 3.0 Dual-Role Device
• High-Speed USB 2.0 Dual-Role Device
• High-Speed USB 2.0 On-The-Go

• Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
• PCI Express® 3.0 Subsystems With Two 5-Gbps Lanes
• One 2-lane Gen2-CompliantPort
• or Two 1-lane Gen2-Compliant Ports
• Dual Controller Area Network (DCAN) Modules
• CAN 2.0BProtocol

• MIPI® CSI-2 Camera Serial Interface
• Up to 215 General-Purpose I/O (GPIO) Pins

• Power, Reset, and Clock Management

• On-Chip Debug With CTools Technology
• 28-nm CMOS Technology

• 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)
All trademarks are the property of their respective owners.