LDB103S

Marking：DB-LS；SINGLE-PHASE GLASS PASSIVATED SILICON BRIDGE RECTIFIER VOLTAGE RANGE 50 to 1000 Volts CURRENT 1.0 Ampere

FEATURES *Goodforautomationinsertion *Idealforprintedcircuitboard *Reliablelowcostconstructionutilizingmolded *Glasspassivateddevice *Polaritysymbolsmoldedonbody *Mountingposition:Any

LDB104S

Marking：DB-LS；SINGLE-PHASE GLASS PASSIVATED SILICON BRIDGE RECTIFIER VOLTAGE RANGE 50 to 1000 Volts CURRENT 1.0 Ampere

FEATURES *Goodforautomationinsertion *Idealforprintedcircuitboard *Reliablelowcostconstructionutilizingmolded *Glasspassivateddevice *Polaritysymbolsmoldedonbody *Mountingposition:Any

LDB105S

Marking：DB-LS；SINGLE-PHASE GLASS PASSIVATED SILICON BRIDGE RECTIFIER VOLTAGE RANGE 50 to 1000 Volts CURRENT 1.0 Ampere

FEATURES *Goodforautomationinsertion *Idealforprintedcircuitboard *Reliablelowcostconstructionutilizingmolded *Glasspassivateddevice *Polaritysymbolsmoldedonbody *Mountingposition:Any

LDB106S

Marking：DB-LS；SINGLE-PHASE GLASS PASSIVATED SILICON BRIDGE RECTIFIER VOLTAGE RANGE 50 to 1000 Volts CURRENT 1.0 Ampere

FEATURES *Goodforautomationinsertion *Idealforprintedcircuitboard *Reliablelowcostconstructionutilizingmolded *Glasspassivateddevice *Polaritysymbolsmoldedonbody *Mountingposition:Any

LDB107S

Marking：DB-LS；SINGLE-PHASE GLASS PASSIVATED SILICON BRIDGE RECTIFIER VOLTAGE RANGE 50 to 1000 Volts CURRENT 1.0 Ampere

FEATURES *Goodforautomationinsertion *Idealforprintedcircuitboard *Reliablelowcostconstructionutilizingmolded *Glasspassivateddevice *Polaritysymbolsmoldedonbody *Mountingposition:Any

LMKDB1102REYR

Marking：DB1102；Package：VQFN；LMKDB1xxx PCIe Gen 1 to Gen 6 Ultra Low Jitter 1:20, 1:8, 1:4, 1:2, 2:4, 2:2 LP-HCSL Clock Buffer and Clock MUX

1Features •LP-HCSLclockbufferandclockMUXthatsupport: –PCIeGen1toGen6 –CC(CommonClock)andIR(Independent Reference)PCIearchitectures –InputclockwithorwithoutSSC •DB2000QLcompliant: –AlldevicesmeetDB2000QLspecifications –LMKDB1120ispin-compatibletoDB20

LMKDB1102REYT

Marking：DB1102；Package：VQFN；LMKDB1xxx PCIe Gen 1 to Gen 6 Ultra Low Jitter 1:20, 1:8, 1:4, 1:2, 2:4, 2:2 LP-HCSL Clock Buffer and Clock MUX

1Features •LP-HCSLclockbufferandclockMUXthatsupport: –PCIeGen1toGen6 –CC(CommonClock)andIR(Independent Reference)PCIearchitectures –InputclockwithorwithoutSSC •DB2000QLcompliant: –AlldevicesmeetDB2000QLspecifications –LMKDB1120ispin-compatibletoDB20

LMKDB1202REYR

Marking：DB1202；Package：VQFN；LMKDB1xxx PCIe Gen 1 to Gen 6 Ultra Low Jitter 1:20, 1:8, 1:4, 1:2, 2:4, 2:2 LP-HCSL Clock Buffer and Clock MUX

1Features •LP-HCSLclockbufferandclockMUXthatsupport: –PCIeGen1toGen6 –CC(CommonClock)andIR(Independent Reference)PCIearchitectures –InputclockwithorwithoutSSC •DB2000QLcompliant: –AlldevicesmeetDB2000QLspecifications –LMKDB1120ispin-compatibletoDB20

LMKDB1202REYT

Marking：DB1202；Package：VQFN；LMKDB1xxx PCIe Gen 1 to Gen 6 Ultra Low Jitter 1:20, 1:8, 1:4, 1:2, 2:4, 2:2 LP-HCSL Clock Buffer and Clock MUX

1Features •LP-HCSLclockbufferandclockMUXthatsupport: –PCIeGen1toGen6 –CC(CommonClock)andIR(Independent Reference)PCIearchitectures –InputclockwithorwithoutSSC •DB2000QLcompliant: –AlldevicesmeetDB2000QLspecifications –LMKDB1120ispin-compatibletoDB20

MAX6314US37D2-T

Marking：DB**；Package：SOT-143；68HC11/Bidirectional-Compatible 關P Reset Circuit

GeneralDescription TheMAX6314low-powerCMOSmicroprocessor(µP)supervisorycircuitisdesignedtomonitorpowersuppliesinµPanddigitalsystems.TheMAX6314’sRESEToutputisbidirectional,allowingittobedirectlyconnectedtoµPswithbidirectionalresetinputs,suchasthe68HC11.I