CY7C1350F中文资料赛普拉斯数据手册PDF规格书

Functional Description[1]

The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.

Features

• Pin compatible and functionally equivalent to ZBT™ devices

• Internally self-timed output buffer control to eliminate the need to use OE

• Byte Write capability

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• 2.5V/3.3V I/O Operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE)

• JEDEC-standard 100 TQFP and 119 BGA packages

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep mode option