CY7C1350B-100AC中文资料赛普拉斯数据手册PDF规格书

Functional Description

The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1350B is pin/functionally compatible to ZBT SRAMs IDT71V546, MT55L128L36P, and MCM63Z736.

Features

• Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736

• Supports 166-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate the need to use OE

• Fully registered (inputs and outputs) for pipelined operation

• Byte Write capability

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 3.8 ns (for 150-MHz device)

— 4.0 ns (for 143-MHz device)

— 4.2 ns (for 133-MHz device)

— 5.0 ns (for 100-MHz device)

— 7.0 ns (for 80-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

• Low standby power (17.325 mW max.)