18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

文件：257.709 Kbytes 页数：24 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：515.89 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：1.71052 Mbytes 页数：31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)\n• 300-MHz clock for high bandwidth\n• 2-Word burst for reducing address bus frequency\n• Double Data Rate (DDR) interfaces\n   (data transferred at 600 MHz) @ 300 MHz\n• Two input clocks (K and K) for precise DDR timing\n   — SRAM uses rising e;

Infineon

英飞凌

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

文件：257.709 Kbytes 页数：24 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

文件：257.709 Kbytes 页数：24 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

文件：257.709 Kbytes 页数：24 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：1.71052 Mbytes 页数：31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：515.89 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：515.89 Kbytes 页数：28 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司