18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：1.35322 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：1.35322 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：1.35322 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：1.35322 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：1.35322 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：1.35322 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：1.35322 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：1.35322 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Errata Document for CY7C1312V18 & CY7C1314V18

Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：47.58 Kbytes 页数：5 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Errata Document for CY7C1312V18 & CY7C1314V18

Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：47.58 Kbytes 页数：5 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司