首页 >CSSSTUA32S869BH(LF)-T>规格书列表
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14-BitConfigurableRegisteredBufferforDDR2 GeneralDescription TheICSSSTUA32S869Bis14-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation.AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversoptimizedtodrivethe | ICST Integrated Circuit Systems | ICST | ||
14-BitConfigurableRegisteredBufferforDDR2 RecommendedApplication: •DDR2MemoryModules •ProvidescompleteDDRDIMMsolutionwith ICS97U877 •IdealforDDR2400,533and667 ProductFeatures: •14-bit1:2registeredbufferwithparitycheck functionality •SupportsSSTL_18JEDECspecificationondata inputsandoutputs •50mo | RENESASRenesas Technology Corp 瑞萨瑞萨科技有限公司 | RENESAS | ||
14-BitConfigurableRegisteredBufferforDDR2 RecommendedApplication: •DDR2MemoryModules •ProvidescompleteDDRDIMMsolutionwith ICS97U877 •IdealforDDR2400,533and667 ProductFeatures: •14-bit1:2registeredbufferwithparitycheck functionality •SupportsSSTL_18JEDECspecificationondata inputsandoutputs •50mo | RENESASRenesas Technology Corp 瑞萨瑞萨科技有限公司 | RENESAS |
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