丝印：CM508B；Package：TSSOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CM508B；Package：TSSOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

HIGH EFFICIENCY RECTIFIERS(5.0A,600-1000V)

文件：123.97 Kbytes 页数：2 Pages

MOSPEC

统懋

Silicon MOS IC

文件：30.85 Kbytes 页数：2 Pages

PANASONIC

松下

SCHOTTKY BARRIER RECTIFIERS(5.0A,70-100V)

Schottky Barrier Rectifiers Using the Schottky Barrier principle with a Molybdenum barrier metal. These state-of-the-art geometry features epitaxial construction with oxide passivation and metal overlay contact. Ideally suited for low voltage, high frequency rectification, or as free wheeling and

文件：231.04 Kbytes 页数：3 Pages

MOSPEC

统懋