74LVC1G125DCKTG4

Marking：CM5；Package：SC70；Single Bus Buffer Gate With 3-State Output

SN74LVC1G125DCKJ

Marking：CM5；Package：SC70；Single Bus Buffer Gate With 3-State Output

SN74LVC1G125DCKR

Marking：CM5；Package：SC70；Single Bus Buffer Gate With 3-State Output

SN74LVC1G125DCKT

Marking：CM5；Package：SC70；Single Bus Buffer Gate With 3-State Output

CD4504BPW

Marking：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: »Independenceofpower-supplysequence considerations-VeccanexceedVoo; inputsignalscanexceedbothVccandVoo ®Upanddownlevel-shiftingcapability =Shiftableinputthresholdforeither CMOSorTTLcompatibility =Standardizedsymmetricaloutput characteristics =100&#

CD4504BPW.A

Marking：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: »Independenceofpower-supplysequence considerations-VeccanexceedVoo; inputsignalscanexceedbothVccandVoo ®Upanddownlevel-shiftingcapability =Shiftableinputthresholdforeither CMOSorTTLcompatibility =Standardizedsymmetricaloutput characteristics =100&#

CD4504BPWE4

Marking：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: »Independenceofpower-supplysequence considerations-VeccanexceedVoo; inputsignalscanexceedbothVccandVoo ®Upanddownlevel-shiftingcapability =Shiftableinputthresholdforeither CMOSorTTLcompatibility =Standardizedsymmetricaloutput characteristics =100&#

CD4504BPWR

Marking：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: »Independenceofpower-supplysequence considerations-VeccanexceedVoo; inputsignalscanexceedbothVccandVoo ®Upanddownlevel-shiftingcapability =Shiftableinputthresholdforeither CMOSorTTLcompatibility =Standardizedsymmetricaloutput characteristics =100&#

CD4504BPWR.A

Marking：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: »Independenceofpower-supplysequence considerations-VeccanexceedVoo; inputsignalscanexceedbothVccandVoo ®Upanddownlevel-shiftingcapability =Shiftableinputthresholdforeither CMOSorTTLcompatibility =Standardizedsymmetricaloutput characteristics =100&#

CD4508BPW

Marking：CM508B；Package：TSSOP；CMOS Dual 4-Bit Latch

Features: ®Twoindependent4-bitlatches ®Individualmasterresetforeach4-bitlatch ®3.stateoutputswithhigh-impedancestateforbus lineapplications =Medium-speedoperation:tp=tp4=70ns {typ.)atVpp=10VandC_=50pF ®100%testedforquiescentcurrentat20V ®5-V