3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：166.43 Kbytes 页数：13 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes 页数：18 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：551.76 Kbytes 页数：17 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes 页数：18 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes 页数：18 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes 页数：18 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes 页数：18 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：551.76 Kbytes 页数：17 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes 页数：18 Pages

TI

德州仪器

具有断电模式的 3.3V 锁相环路时钟驱动器

The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchrono • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1\n• Spread Spectrum Clock Compatible\n• Operating Frequency 20 MHz to 175 MHz\n• Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps\n• Jitter (cyc–cyc) at 66 MHz to 166 MHz is |70| ps\n• Advanced Deep Submic;

TI

德州仪器