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CDCVF2510中文资料适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器数据手册TI规格书

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厂商型号

CDCVF2510

参数属性

CDCVF2510 封装/外壳为24-TSSOP(0.173",4.40mm 宽);包装为卷带(TR);类别为集成电路(IC)的时钟发生器PLL频率合成器;产品描述:IC 3.3V PLL CLK-DRVR 24-TSSOP

功能描述

适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器

封装外壳

24-TSSOP(0.173",4.40mm 宽)

制造商

TI Texas Instruments

中文名称

德州仪器 美国德州仪器公司

数据手册

下载地址下载地址二

更新时间

2025-9-26 17:06:00

人工找货

CDCVF2510价格和库存,欢迎联系客服免费人工找货

CDCVF2510规格书详情

描述 Description

The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCVF2510 is characterized for operation from 0°C to 85°C. For application information see the application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL With Spread Spectrum Clocking (SSC) (SCAA039).

特性 Features

• Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
• Operating Frequency 50 MHz to 175 MHz
• Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps
• Available in Plastic 24-Pin TSSOP
• Distributes One Clock Input to One Bank of 10 Outputs
• 25- On-Chip Series Damping Resistors
• Operates at 3.3 V
NOT RECOMMENDED FOR NEW DESIGNS USE CDCVF2510A AS A REPLACEMENT

技术参数

  • 制造商编号

    :CDCVF2510

  • 生产厂家

    :TI

  • Additive RMS jitter (Typ) (fs)

    :70

  • Output frequency (Max) (MHz)

    :175

  • Number of outputs

    :10

  • Output supply voltage (V)

    :3.3

  • Core supply voltage (V)

    :3.3

  • Output skew (ps)

    :100

  • Features

    :SDR

  • Operating temperature range (C)

    :0 to 85

  • Rating

    :Catalog

  • Output type

    :LVTTL

  • Input type

    :LVTTL

供应商 型号 品牌 批号 封装 库存 备注 价格
TI
24+
TSSOP|24
279100
免费送样原盒原包现货一手渠道联系
询价
TI/德州仪器
22+
TSSOP24
12245
现货,原厂原装假一罚十!
询价
TI/德州仪器
21+
TSSOP24
2000
百域芯优势 实单必成 可开13点增值税
询价
TI/BB
19+
面谈
6000
TSSOP24
询价
TI
24+
TSSOP24
30000
TI一级代理商专营进口原装现货假一赔十
询价
TI/德州仪器
22+
TSSOP-24
8000
原装正品支持实单
询价
TI/BB
25+
QFP
3200
全新原装、诚信经营、公司现货销售!
询价
TI/德州仪器
21+
TSSOP24
36680
只做原装,质量保证
询价
TI
23+
TSOP
7000
绝对全新原装!100%保质量特价!请放心订购!
询价
TI
24+
TSSOP-24
23
询价