CDCU2A877数据手册集成电路(IC)的应用特定时钟/定时规格书PDF

厂商型号 |
CDCU2A877 |
参数属性 | CDCU2A877 封装/外壳为52-VFBGA;包装为卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带;类别为集成电路(IC)的应用特定时钟/定时;产品描述:1.8V PHASE-LOCK LOOP CLOCK DRIVE |
功能描述 | 适用于 DDR2 SDRAM 应用且具有高输出驱动的 1.8V 锁相环路时钟驱动器 |
封装外壳 | 52-VFBGA |
制造商 | TI Texas Instruments |
中文名称 | 德州仪器 美国德州仪器公司 |
原厂标识 | TI |
数据手册 | |
更新时间 | 2025-8-5 23:01:00 |
人工找货 | CDCU2A877价格和库存,欢迎联系客服免费人工找货 |
CDCU2A877规格书详情
描述 Description
The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.
特性 Features
• 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate ( DDR II ) Applications
• Spread Spectrum Clock Compatible
• Operating Frequency: 125 MHz to 410 MHz
• Application Frequency: 160 MHz to 410 MHz
• Low Jitter (Cycle-Cycle): ±40 ps
• Low Output Skew: 35 ps
• Stabilization Time FBIN ) are Used to Synchronize the Outputs to the Input Clocks
• Meets or Exceeds CUA877/CUA878 Specification PLL Standard for PC2-3200/4300/5300/6400
• Fail-Safe Inputs
MicroStar Junior is a trademark of Texas Instruments.
技术参数
- 制造商编号
:CDCU2A877
- 生产厂家
:TI
- Additive RMS jitter (Typ) (fs)
:40
- Output frequency (Max) (MHz)
:410
- Number of outputs
:10
- Output supply voltage (V)
:1.8
- Core supply voltage (V)
:1.8
- Output skew (ps)
:30
- Features
:Spread spectrum clocking (SSC)
- Operating temperature range (C)
:0 to 70
- Rating
:Catalog
- Output type
:LVCMOS
- Input type
:LVCMOS
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
TI/德州仪器 |
24+ |
NA/ |
150 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
TI(德州仪器) |
24+ |
BGA52(4.5x7) |
7350 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
询价 | ||
TI |
20+ |
BGA |
53650 |
TI原装主营-可开原型号增税票 |
询价 | ||
TI |
23+ |
NA |
20000 |
全新原装假一赔十 |
询价 | ||
TI/德州仪器 |
22+ |
BGA-52 |
100000 |
代理渠道/只做原装/可含税 |
询价 | ||
TI |
8 |
BGA-52 |
985 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
询价 | ||
22+ |
5000 |
询价 | |||||
TI |
22+ |
52-BGA |
5000 |
全新原装,力挺实单 |
询价 | ||
TI |
23+ |
NA |
20000 |
询价 | |||
TI |
705 |
477 |
原装正品 |
询价 |