CDCLVP2104RHDR集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

CDCLVP2104RHDR属于集成电路（IC）的时钟缓冲器驱动器。由德州仪器制造生产的CDCLVP2104RHDR时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

1 Features

1• Dual 1:4 Differential Buffer

• Two Clock Inputs

• Universal Inputs Can Accept LVPECL, LVDS,

LVCMOS/LVTTL

• Eight LVPECL Outputs

• Maximum Clock Frequency: 2 GHz

• Maximum Core Current Consumption: 78 mA

• Very Low Additive Jitter: <100 fs, RMS in 10-kHz

to 20-MHz Offset Range

• 2.375-V to 3.6-V Device Power Supply

• Maximum Propagation Delay: 450 ps

• Maximum 15 ps Within Bank Output Skew

• LVPECL Reference Voltage, VAC_REF, Available

for Capacitive-Coupled Inputs

• Industrial Temperature Range: –40°C to +85°C

• Supports 105°C PCB Temperature (Measured

with a Thermal Pad)

• Available in 5-mm × 5-mm, 28-Pin VQFN (RHD)

Package

• ESD Protection Exceeds 2000 V (HBM)

2 Applications

• Wireless Communications

• Telecommunications/Networking

• Medical Imaging

• Test and Measurement Equipment

3 Description

The CDCLVP2104 is a highly versatile, low additive

jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS

inputs for a variety of communication applications. It

has a maximum clock frequency up to 2 GHz. Each

buffer block consists of one input that feeds two

LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to

20 MHz, and overall output skew is as low as 15 ps,

making the device a perfect choice for use in

demanding applications.

The CDCLVP2104 clock buffer distributes two clock

inputs (IN0, IN1) to eight pairs of differential LVPECL

clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one

input that feeds two LVPECL clock outputs. The

inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2104 is specifically designed for driving

50-Ω transmission lines. When driving the inputs in

single-ended mode, the LVPECL bias voltage

(VAC_REF) must be applied to the unused negative

input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2104 is characterized for operation from

–40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.