1:10 LVPECL/HSTL 至 LVPECL 时钟驱动器

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The • Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock Outputs\n• Fully Compatible With LVECL/LVPECL/HSTL\n• Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply\n• Selectable Clock Input Through CLK_SEL\n• Low-Output Skew (Typ 15 ps) for Clock-Distribution Ap;

TI

德州仪器

CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器

CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：813.21 Kbytes 页数：28 Pages

TI

德州仪器

CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器

丝印：1102；Package：VQFN(RGT)；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器

丝印：1102；Package：VQFN；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：813.21 Kbytes 页数：28 Pages

TI

德州仪器

丝印：1102；Package：VQFN；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：813.21 Kbytes 页数：28 Pages

TI

德州仪器

丝印：1102；Package：VQFN(RGT)；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器

丝印：1102；Package：VQFN(RGT)；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器

丝印：1102；Package：VQFN；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：813.21 Kbytes 页数：28 Pages

TI

德州仪器