CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：813.21 Kbytes 页数：28 Pages

TI

德州仪器

CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

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德州仪器

Two LVPECL Output, High-Performance Clock Buffer

文件：753.48 Kbytes 页数：22 Pages

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德州仪器

低抖动 1:2 通用至 LVPECL 缓冲器

The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than • 1:2 Differential Buffer\n• Single Clock Input\n• Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL\n• Two LVPECL Outputs\n• Maximum Clock Frequency: 2 GHz\n• Maximum Core Current Consumption: 33 mA\n• Very Low Additive Jitter: to 20-MHz Offset Range\n• 2.375-V to 3.6-V Device Power Supply\n• ;

TI

德州仪器

CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器

丝印：1102；Package：VQFN(RGT)；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器

丝印：1102；Package：VQFN；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：813.21 Kbytes 页数：28 Pages

TI

德州仪器

丝印：1102；Package：VQFN；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：813.21 Kbytes 页数：28 Pages

TI

德州仪器

丝印：1102；Package：VQFN(RGT)；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器

丝印：1102；Package：VQFN(RGT)；CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer

1 Features 1• 1:2 Differential Buffer • Single Clock Input • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL • Two LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 33 mA • Very Low Additive Jitter:

文件：854.03 Kbytes 页数：31 Pages

TI

德州仪器