CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

1 Features 1• 2:4 Differential Buffer • Low Additive Jitter:

文件：862.08 Kbytes 页数：26 Pages

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CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

1 Features 1• 2:4 Differential Buffer • Low Additive Jitter:

文件：866.49 Kbytes 页数：27 Pages

TI

德州仪器

2:4 Low Additive Jitter LVDS Buffer

文件：918.5 Kbytes 页数：20 Pages

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低抖动 2 路输入可选 1:4 通用至 LVDS 缓冲器

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, L • 2:4 Differential Buffer\n• Industrial Temperature Range: –40°C to 85°C\n• ESD Protection Exceeds 3 kV HBM, 1 kV CDM\n• Telecommunications and Networking\n• Test and Measurement Equipment\n• General Purpose Clocking\n \n All other trademarks are the property of their respective owners;

TI

德州仪器

CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

1 Features 1• 2:4 Differential Buffer • Low Additive Jitter:

文件：866.49 Kbytes 页数：27 Pages

TI

德州仪器

丝印：D1204；Package：VQFN；CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

1 Features 1• 2:4 Differential Buffer • Low Additive Jitter:

文件：862.08 Kbytes 页数：26 Pages

TI

德州仪器

丝印：D1204；Package：VQFN(RGT)；CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

1 Features 1• 2:4 Differential Buffer • Low Additive Jitter:

文件：866.49 Kbytes 页数：27 Pages

TI

德州仪器

丝印：D1204；Package：VQFN(RGT)；CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

1 Features 1• 2:4 Differential Buffer • Low Additive Jitter:

文件：866.49 Kbytes 页数：27 Pages

TI

德州仪器

丝印：D1204；Package：VQFN；CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

1 Features 1• 2:4 Differential Buffer • Low Additive Jitter:

文件：862.08 Kbytes 页数：26 Pages

TI

德州仪器

丝印：D1204；Package：VQFN(RGT)；CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer

1 Features 1• 2:4 Differential Buffer • Low Additive Jitter:

文件：866.49 Kbytes 页数：27 Pages

TI

德州仪器