CDCLVD1204中文资料低抖动 2 路输入可选 1:4 通用至 LVDS 缓冲器数据手册TI规格书

描述 Description

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

特性 Features

• 2:4 Differential Buffer
• Industrial Temperature Range: –40°C to 85°C
• ESD Protection Exceeds 3 kV HBM, 1 kV CDM
• Telecommunications and Networking
• Test and Measurement Equipment
• General Purpose Clocking

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