CDCF5801A中文资料具有低至 10ps 以下可编程延迟线路的低抖动、基于 PLL 的倍频器和分频器数据手册TI规格书

描述 Description

The CDCF5801A provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin, while strapping the LEADLAG pin to dc high or low. Further possible applications are:Aligning the rising edge of the output clock signal to the input clock rising edge Avoiding PLL instability in applications that require very long PLL feedback lines Isolation of jitter and digital switching noise Limitation of jitter in systems with good ppm frequency stability The CDCF5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions.The CDCF5801A provides clock multiplication and division from a reference clock (REFCLK) signal. The device is optimized to have extremely low jitter impact from input to output. The predivider pins MULT[0:1] and post-divider pins P[0:2] provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 25 MHz to 280 MHz with clock input references (REFCLK) ranging from 12.5 MHz to 240 MHz. See for detailed frequency support. The selection of pins MULT[0:1] and P[1:2] determines the multiplication value of 1, 2, 4, or 8. The CDCF5801A offers several power-down/ high-impedance modes, selectable by pins P0, STOPB and PWRDN. Another unique capability of the CDCF5801A is the high sensitivity and wide common-mode range of the clock-input pin REFCLK by varying the voltage on the VDDREF pin. The clock signal outputs CLKOUT and CLKOUTB can be used independently to generate single-ended clock signals. The CLKOUT/CLKOUTB outputs can also be combined to generate a differential output signal suitable for LVDS, LVPECL, or HSTL/SSTL signaling. The CDCF5801A is characterized for operation over free-air temperatures of -40°C to 85°C.

特性 Features

• Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8
• Fail-Safe Power Up Initialization
• Programmable Bidirectional Delay Steps of 1.3 mUI
• Output Frequency Range of 25 MHz to 280 MHz
• Input Frequency Range of 12.5 MHz to 240 MHz
• Low Jitter Generation
• Single-Ended REFCLK Input With Adjustable Trigger Level (Works With LVTTL, HSTL, and LVPECL)
• Differential/Single-Ended Output
• Output Can Drive LVPECL, LVDS, and LVTTL
• Three Power Operating Modes to Minimize Power
• Low Power Consumption (

简介

CDCF5801A属于集成电路（IC）的时钟发生器PLL频率合成器。由TI制造生产的CDCF5801A时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。