3.3 V Clock Synthesizer for DLP™ Systems

FEATURES · High-Performance Clock Synthesizer · Uses a 20 MHz Crystal Input to Generate Multiple Output Frequencies · Integrated Load Capacitance for 20 MHz Oscillator Reducing System Cost · All PLL Loop Filter Components are Integrated · Generates the Following Clocks: – REF CLK 20 MHz (

文件：339.21 Kbytes 页数：10 Pages

TI

德州仪器

3.3 V Clock Synthesizer for DLP Systems

文件：528.45 Kbytes 页数：10 Pages

TI

德州仪器

3.3 V Clock Synthesizer for DLP Systems

文件：205.19 Kbytes 页数：9 Pages

TI

德州仪器

3.3 V Clock Synthesizer for DLP TM Systems

文件：147.99 Kbytes 页数：7 Pages

TI

德州仪器

用于 DLP 系统的 3.3V 时钟合成器

The CDCDLP223 is a PLL-based high performance clock synthesizer that is optimized for use in DLP™ systems. It uses a 20 MHz crystal to generate the fundamental frequency and derives the frequencies for the 100 MHz HCLK and the 300 MHz HCLK output. Further, the CDCDLP223 generates a buffered copy of • High-Performance Clock Synthesizer\n• Uses a 20 MHz Crystal Input to Generate Multiple Output Frequencies\n• Integrated Load Capacitance for 20 MHz Oscillator Reducing System Cost\n• All PLL Loop Filter Components are Integrated\n• Generates the Following Clocks: \n• REF CLK 20 MHz (Buffered) \n• ;

TI

德州仪器

3.3 V Clock Synthesizer for DLP™ Systems

FEATURES · High-Performance Clock Synthesizer · Uses a 20 MHz Crystal Input to Generate Multiple Output Frequencies · Integrated Load Capacitance for 20 MHz Oscillator Reducing System Cost · All PLL Loop Filter Components are Integrated · Generates the Following Clocks: – REF CLK 20 MHz (

文件：339.21 Kbytes 页数：10 Pages

TI

德州仪器

3.3 V Clock Synthesizer for DLP™ Systems

FEATURES · High-Performance Clock Synthesizer · Uses a 20 MHz Crystal Input to Generate Multiple Output Frequencies · Integrated Load Capacitance for 20 MHz Oscillator Reducing System Cost · All PLL Loop Filter Components are Integrated · Generates the Following Clocks: – REF CLK 20 MHz (

文件：339.21 Kbytes 页数：10 Pages

TI

德州仪器

3.3 V Clock Synthesizer for DLP Systems

文件：205.19 Kbytes 页数：9 Pages

TI

德州仪器

3.3 V Clock Synthesizer for DLP Systems

文件：528.45 Kbytes 页数：10 Pages

TI

德州仪器

3.3 V Clock Synthesizer for DLP Systems

文件：528.45 Kbytes 页数：10 Pages

TI

德州仪器