CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI

德州仪器

LOW PHASE-NOISE TWO-CHANNEL CLOCK FAN-OUT BUFFER

文件：750.82 Kbytes 页数：15 Pages

TI

德州仪器

双通道方波/正弦-方波时钟缓冲器

CDC3RL02 是一款双通道时钟扇出缓冲器，非常适用于需要时钟缓冲且具有最小附加相位噪声和扇出功能的便携式终端设备（如手机）。该器件将温度补偿晶体振荡器 (TCXO) 等单个主时钟缓冲至多个外设。该器件具有两个时钟请求输入（CLK_REQ1 和 CLK_REQ2），其中每个输入均支持单个时钟输出。\n\nCDC3RL02 在主时钟输入 (MCLK_IN) 处接受方波或正弦波，无需交流耦合电容器。可接受的最小正弦波为 0.3V 信号（峰峰值）。CDC3RL02 旨在提供极小的通道间偏差、附加输出抖动和附加相位噪声。自适应时钟输出缓冲器可在宽电容负荷范围内提供受控的转换率，从而更大限度地降低 E • 低附加噪声： \n• 10kHz 偏移相位噪声时为 –149dBc/Hz \n• 0.37ps (RMS) 输出抖动\n \n• 限制输出转换率可降低 EMI（对于 10pF 至 50pF 的负载，上升/下降时间为 1ns 至 5ns）\n• 自适应输出级控制反射\n• 稳压 1.8V 外部可用 I/O 电源\n• 超小型 8 凸点 YFP 0.4mm 间距 WCSP（0.8mm × 1.6mm）\n• ESD 性能超过 JESD 22 \n• 2000V 人体放电模型 (A114-A)\n• 1000V 带电器件模型（JESD22-C101-A III 级）;

TI

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI

德州仪器

Low Phase-Noise Two-Channel Clock Fan-Out Buffer

文件：820.58 Kbytes 页数：20 Pages

TI

德州仪器