丝印：CDC208；Package：SOIC；DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted C

文件：624.32 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CDC208；Package：SOIC；DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted C

文件：624.32 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CDC208；Package：SOIC；DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted C

文件：624.32 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CDC208；Package：SOP；DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted C

文件：624.32 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CDC208；Package：SOP；DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted C

文件：624.32 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CDC208；Package：SOP；DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted C

文件：624.32 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CDC208；Package：SOP；DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted C

文件：624.32 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC LVTTL-Compatible Inputs and Outputs Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Distributes One Clock Input to Ten Outputs Outputs Have In

文件：298.3 Kbytes 页数：14 Pages

TI

德州仪器

丝印：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC LVTTL-Compatible Inputs and Outputs Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Distributes One Clock Input to Ten Outputs Outputs Have In

文件：298.3 Kbytes 页数：14 Pages

TI

德州仪器

丝印：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC LVTTL-Compatible Inputs and Outputs Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Distributes One Clock Input to Ten Outputs Outputs Have In

文件：298.3 Kbytes 页数：14 Pages

TI

德州仪器