丝印：CDC；Package：SC-62；20 V, 2 A NPN medium power transistors

Features and benefits  High current  Two current gain selections  High power dissipation capability  Exposed heatsink for excellent thermal and electrical conductivity (SOT89, SOT1061)  Leadless very small SMD plastic package with medium power capability (SOT1061)  AEC-Q101 qualified

文件：2.12979 Mbytes 页数：23 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：CDC；Package：SOT-89；Plastic-Encapsulate NPN Transistors

FEATURES • High current：1A • PD Power Dissipation:500mW

文件：1.46887 Mbytes 页数：2 Pages

SKTECHNOLGYSHIKE Electronics

时科广东时科微实业有限公司

丝印：CDC；Package：SC-62；20 V, 2 A NPN medium power transistors

Features and benefits • High collector current capability IC and ICM • Two current gain selections • High power dissipation capability • Qualified according to AEC-Q101 and recommended for use in automotive applications

文件：235.48 Kbytes 页数：12 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：CDC203；Package：SOIC；3.3-V HEX INVERTER/CLOCK DRIVER

Replaces 74AC11203 Low-Skew Propagation Delay Specifications for Clock Driver Applications Operates at 3.3-V VCC Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-μm

文件：171.37 Kbytes 页数：8 Pages

TI2

德州仪器

丝印：CDC203；Package：SOIC；3.3-V HEX INVERTER/CLOCK DRIVER

Replaces 74AC11203 Low-Skew Propagation Delay Specifications for Clock Driver Applications Operates at 3.3-V VCC Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-μm

文件：171.37 Kbytes 页数：8 Pages

TI2

德州仪器

丝印：CDC203；Package：SOIC；3.3-V HEX INVERTER/CLOCK DRIVER

Replaces 74AC11203 Low-Skew Propagation Delay Specifications for Clock Driver Applications Operates at 3.3-V VCC Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-μm

文件：171.37 Kbytes 页数：8 Pages

TI2

德州仪器

丝印：CDC204；Package：SOIC；HEX INVERTER/CLOCK DRIVER

CDC204 Replaces 74AC11204 Low-Skew Propagation Delay Specifications for Clock-Driver Applications CMOS-Compatible Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC E (Enhanced-Performance Im

文件：175.1 Kbytes 页数：8 Pages

TI2

德州仪器

丝印：CDC204；Package：SOIC；HEX INVERTER/CLOCK DRIVER

CDC204 Replaces 74AC11204 Low-Skew Propagation Delay Specifications for Clock-Driver Applications CMOS-Compatible Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC E (Enhanced-Performance Im

文件：175.1 Kbytes 页数：8 Pages

TI2

德州仪器

丝印：CDC204；Package：SOIC；HEX INVERTER/CLOCK DRIVER

CDC204 Replaces 74AC11204 Low-Skew Propagation Delay Specifications for Clock-Driver Applications CMOS-Compatible Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC E (Enhanced-Performance Im

文件：175.1 Kbytes 页数：8 Pages

TI2

德州仪器

丝印：CDC208；Package：SOIC；DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted C

文件：624.32 Kbytes 页数：17 Pages

TI2

德州仪器