丝印：HJ377；Package：TSSOP；High-Speed CMOS Logic Octal D-Type Flip-Flop With Data Enable

Features • Buffered Common Clock • Buffered Inputs • Typical Propagation Delay at CL = 15pF, VCC = 5V, TA = 25oC - 14 ns (HC Types - 16 ns (HCT Types) • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . .

文件：789.89 Kbytes 页数：20 Pages

TI

德州仪器

Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：58.7 Kbytes 页数：9 Pages

HitachiHitachi Semiconductor

日立日立公司

Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

RENESAS

瑞萨

Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

RENESAS

瑞萨