丝印：CD74HC195E；Package：PDIP；High-Speed CMOS Logic 4-Bit Parallel Access Register

Features • Asynchronous Master Reset • J, K, (D) Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfer • Shift Right and Parallel Load Capability • Complementary Output From Last Stage • Buffered Inputs • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout

文件：665.93 Kbytes 页数：20 Pages

TI

德州仪器

High Speed CMOS Logic 4-Bit Parallel Access Register

文件：42.23 Kbytes 页数：6 Pages

TI

德州仪器

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：335.19 Kbytes 页数：11 Pages

TI

德州仪器

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：341.18 Kbytes 页数：13 Pages

TI

德州仪器