丝印：CD54ACT109F3A；Package：CDIP；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：412.14 Kbytes 页数：14 Pages

TI

德州仪器

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：412.14 Kbytes 页数：14 Pages

TI

德州仪器

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：337.77 Kbytes 页数：10 Pages

TI

德州仪器

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：349.71 Kbytes 页数：11 Pages

TI

德州仪器