CD54AC163F3A

Marking：CD54AC163F3A；Package：CDIP；4-BIT SYNCHRONOUS BINARY COUNTERS

InternalLook-AheadforFastCounting CarryOutputforn-BitCascading SynchronousCounting SynchronouslyProgrammable description/orderinginformation The’AC163devicesare4-bitbinarycounters. Thesesynchronous,presettablecountersfeature aninternalcarrylook-aheadforapplicatio

CD54AC163F3A.A

Marking：CD54AC163F3A；Package：CDIP；4-BIT SYNCHRONOUS BINARY COUNTERS

InternalLook-AheadforFastCounting CarryOutputforn-BitCascading SynchronousCounting SynchronouslyProgrammable description/orderinginformation The’AC163devicesare4-bitbinarycounters. Thesesynchronous,presettablecountersfeature aninternalcarrylook-aheadforapplicatio

CD54AC280F3A

Marking：CD54AC280F3A；Package：CDIP；9-Bit Odd/Even Parity Generator/Checker

Features •BufferedInputs •TypicalPropagationDelay -10nsatVCC=5V,TA=25oC,CL=50pF •Exceeds2kVESDProtectionperMIL-STD-883, Method3015 •SCR-Latchup-ResistantCMOSProcessandCircuit Design •SpeedofBipolarFAST™/AS/SwithSignificantly ReducedPowerConsumption •B

CD54AC280F3A.A

Marking：CD54AC280F3A；Package：CDIP；9-Bit Odd/Even Parity Generator/Checker

Features •BufferedInputs •TypicalPropagationDelay -10nsatVCC=5V,TA=25oC,CL=50pF •Exceeds2kVESDProtectionperMIL-STD-883, Method3015 •SCR-Latchup-ResistantCMOSProcessandCircuit Design •SpeedofBipolarFAST™/AS/SwithSignificantly ReducedPowerConsumption •B

CD54ACT109F3A

Marking：CD54ACT109F3A；Package：CDIP；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD54ACT109F3A.A

Marking：CD54ACT109F3A；Package：CDIP；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,

CD54ACT112F3A

Marking：CD54ACT112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays 24-mAOutputDriveCurrent Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,Me

CD54ACT112F3A.A

Marking：CD54ACT112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays 24-mAOutputDriveCurrent Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,Me

CD54ACT138F3A

Marking：CD54ACT138F3A；Package：CDIP；CDx4ACT138 3-Line to 8-Line Decoders/Demultiplexers

1Features •InputsareTTL-voltagecompatible •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Designedspecificallyforhigh-speedmemory decodersanddata-transmissionsystems •Incorporatethreeenableinputstosimplify cascadingand/ordatareception •

CD54ACT139F3A

Marking：CD54ACT139F3A；Package：CDIP；DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

ACTypesFeature1.5-Vto5.5-VOperation andBalancedNoiseImmunityat30%ofthe SupplyVoltage BufferedInputs IncorporateTwoEnableInputstoSimplify Cascadingand/orDataReception SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagation