CMOS Dual 64-Stage Static Shift Register

文件：396.35 Kbytes 页数：9 Pages

TI

德州仪器

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes 页数：9 Pages

TI

德州仪器

3-state parallel outputs for connection to common bus

文件：1.11921 Mbytes 页数：14 Pages

TI

德州仪器

CMOS Dual 64-Stage Static Shift Register

文件：396.35 Kbytes 页数：9 Pages

TI

德州仪器

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes 页数：9 Pages

TI

德州仪器

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes 页数：9 Pages

TI

德州仪器

CMOS Dual 64-Stage Static Shift Register

文件：396.35 Kbytes 页数：9 Pages

TI

德州仪器

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes 页数：9 Pages

TI

德州仪器

CMOS 双路 64 级静态移位寄存器

CD4517B dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32nd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, an • Low quiescent current - 10 nA/pkg (typ.) at VDD = 5 V• Clock frequency 12 MHz (typ.) at VDD = 10 V• Schmitt trigger clock inputs allow operation with very slow clock rise and fall times• Capable of driving two low-power TTL loads, one low-power Schottky TTL load, or two HTL loads• Three-state outp;

TI

德州仪器

CD4000系列 逻辑芯片

HGSEMI

华冠