CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation

文件：121.64 Kbytes 页数：8 Pages

SYC

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima rily used in decoding applications where low power dissipa tion

文件：84.97 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima rily used in decoding applications where low power dissipa tion

文件：84.97 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation

文件：121.64 Kbytes 页数：8 Pages

SYC

丝印：7703201JA；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：7703201JA；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4515BM；Package：SOIC；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器