丝印：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

文件：702.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

文件：702.45 Kbytes 页数：16 Pages

TI

德州仪器

CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Intersil’s Satellite Applications Flow™ (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of r

文件：33.24 Kbytes 页数：3 Pages

Intersil

CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

CMOS Dual 4-Bit Latch

Description CD4508BMS dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE controls. With the STROBE line in the high state, the data on the D inputs appear at the corresponding Q outputs provided the DISABLE line is in the low state. Changing the

文件：85.96 Kbytes 页数：9 Pages

Intersil

丝印：CM508B；Package：TSSOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CM508B；Package：TSSOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

CMOS Strobed Hex Inverter/Buffer

文件：506.97 Kbytes 页数：10 Pages

TI

德州仪器

CMOS Strobed Hex Inverter/Buffer

文件：1.12343 Mbytes 页数：15 Pages

TI

德州仪器