丝印：CD4504BM；Package：SOIC；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

文件：702.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4504BM；Package：SOIC；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

文件：702.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4504BM；Package：SOIC；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

文件：702.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4508BD/3；Package：CDIPSB；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BD/3；Package：CDIPSB；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BF3A；Package：CDIP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BF3A；Package：CDIP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器