丝印：CD4508B；Package：SOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4508B；Package：SOP；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

文件：650.82 Kbytes 页数：17 Pages

TI

德州仪器

CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

文件：894.19 Kbytes 页数：19 Pages

TI

德州仪器

丝印：7702002EA；Package：CDIP；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

文件：894.19 Kbytes 页数：19 Pages

TI

德州仪器

丝印：7702002EA；Package：CDIP；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

文件：894.19 Kbytes 页数：19 Pages

TI

德州仪器

CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

文件：894.19 Kbytes 页数：19 Pages

TI

德州仪器

CMOS Strobed Hex Inverter/Buffer

Description CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic “1” on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic “1” on the INHIBIT input swit

文件：81.89 Kbytes 页数：8 Pages

Intersil

丝印：CM502B；Package：TSSOP；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

文件：894.19 Kbytes 页数：19 Pages

TI

德州仪器

丝印：CM502B；Package：TSSOP；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

文件：894.19 Kbytes 页数：19 Pages

TI

德州仪器

Hex Non-Inverting 3-STATE Buffer

General Description The CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers 5

文件：62.46 Kbytes 页数：6 Pages

Fairchild

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