CD4094中文资料CMOS 8-Stage Shift-and-Store Bus Register数据手册Renesas规格书

描述 Description

CD4094BMS is a 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs
may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is
high. Data in the storage register appears at the outputs when ever the OUTPUT-ENABLE signal is high.

特性 Features

• High Voltage Type (20V Rating)
• 3-State Parallel Outputs for Connection to Common Bus
• Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges for Cascading
• Medium Speed Operation - 5MHz at 10V (typ)
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
  - 1V at VDD = 5V
  - 2V at VDD = 10V
  - 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications
• Serial-to-Parallel Data Conversion
• Remote Control Holding Register
• Dual-Rank Shift, Hold, and Bus Applications